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Notification of company relocation

2011.11.15

Dear all:

We are pleased to announce that Jedat Inc. is scheduled to relocate its headquarter office on November 28th, 2011. This relocation was made to improve safety and service for customers.

The new address is as follows. Phone number has not changed.

Address	：	OZAWA Bldg. 3-4-14, Higashi-Nihonbashi, Chuo-ku, Tokyo 103-0004 Japan
TEL	：	+81-3-5847-0312
FAX	：	+81-3-5847-0315
URL	：	https://www.newjedat.arum-net.com/eng

We look forward to seeing you in the new office.

For more information, please contact here
Your continued support and contribution is greatly appreciated.

Truly yours,
Jedat Inc.

Access Map:

Transportation:

• One minute on foot from Exit A3 of
  • Toei Subway Shinjuku Line Bakuro-Yokoyama Station
  • Toei Subway Asakusa Line Higashi-Nihonbashi Station
  • JR Sobu line Bakurocho Station

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Jedat Software “Amper” Certified on STARC’s Mixed-Signal Design Flow “STARCAD-AMS”

2011.3.11

To Help STARC Members Ensure Advanced Mixed-Signal Chip Design

Chuo-ku, Tokyo, March 11, 2011 – Jedat, Inc. (headquarters: Chuo-ku, Tokyo, president & CEO: Shinichi Ishibashi, “Jedat”; Jasdaq: 3841) today announced that Semiconductor Technology and Academic Research Center (STARC)（headquarters: Shin Yokohama, Kohoku-ku, Yokohama, CEO: Katsuhiro Shimohigashi, “STARC”) has certified Amper, Jedat’s automatic placement tool for custom LSI, as the area estimation tool for STARC’s recommended mixed-signal design flow, STARCAD-AMS. Jedat Software “Amper” Certified on STARC’s Mixed-Signal Design Flow “STARCAD-AMS”In the evaluation of the functionality of high accuracy and high speed area estimation for analog blocks, STARC found that Amper was the only tool among several other competitive EDA tools, that sufficiently met STARC’s five criteria.

• 1. Observance of constraints
• 2. Pre-execution operation time of 5 or less minutes
• 3. Automatic placement in 5 or less minutes
• 4. Accurate placement result
• 5. Total placement time including manual correction when necessary

Amper is capable of estimating the area of analog blocks with high accuracy and at high speeds by observing the placement constraints (symmetry, pair, and alignment) registered in the circuit, and by utilizing its high accuracy device placement which takes into account the routing area. With this advanced ability, designers can obtain an extremely accurate floor plan result just as they had intended, in a very short time. Amper not only improves the efficiency of area estimation and floor plan but drastically reduces re-spins and significantly shortens the total design cycle. Amper can be used by plugging into Cadence’s design platform IC6.1.4(OA) as well as running on Jedat’s Alpha-SX design platform.

“In our evaluation, Jedat’s Amper was the only tool that has cleared our demanding targets, proving it is a very practical tool in the analog design field.” Said Mr. Kunihiko Tsuboi, general manager of the Mixed-Signal Development Group, 2nd Development Department at STARC. “Because a high accuracy area estimation result can be obtained quickly by using Amper, a review of the circuit design and specification, and examination of the trade-off with its size can be done at an early stage. This becomes an advantage for customer’s business, and critical re-spins can be prevented. Moreover, because a high accuracy floor plan can be done with short turn-around-time (TAT), re-spins from the layout design are reduced and high quality design can be realized. The final result is the shortening of the period of the entire post-layout verification.”

Custom LSI design including analog/mixed-signal is a critical portion of shortening the total design period of SoC design. Jedat’s goal is to shorten this design period to 1/10th of that when using existing flows. This can be achieved, Jedat believes, by offering a new solution into custom LSI markets while continuing the functional enhancement of a variety of design automation tools, including Amper.

About Amper

– Greatly reduces TAT of layout design through the setting of extensive constraint conditions and automatic device placement features –

Amper is an interactive high quality, high speed automatic device placer. Because it can estimate the routing area by processing the layout data as an abstract expression, it enables optimization while considering aspects of place & route. Devices such as MOS, BJT, resistors, and capacitors, can be placed. Block level and device group placement is possible with the tool. This capability can be applied to a wide variety of design fields, without regard to analog or digital circuit design. Extensive and strong constraint conditions can be automatically extracted in the layout editor, and interactively fixed if necessary. In addition, a high quality placement that considers detailed characteristic of devices can be achieved in a short time by running manual placement and automatic placement (partial placement function) alternately.

Benefits

• High quality and high speed automatic placement
  • High quality placement while considering DC path
  • Automatic optimal size determination by self adjustment features like number of device partitions
  • Area optimization by automatic recognition of WELL electric potential
  • Automatic placement while considering routing area
• High speed processing by a layout abstract expression
• Global routing feature enables placement while considering routing area
• Automatic mirror and rotation of placed devices
• Automatic packing capability of MOS transistors
• Partial placement
• Interactive execution in the layout editor
• Group placement
• Automatic extraction of constraint conditions
• Extensive constraint condition settings
• Automatic execution by change in device shape
• Outline placement specification
• Supports CMOS and BiCMOS process

About STARC

The Semiconductor Technology Academic Research Center, STARC, is a research consortium cofounded by leading Japanese semiconductor companies in December 1995. STARC’s mission is to contribute the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies. For more information, please visit http://www.starc.jp/index-e.html.

Name	:	Semiconductor Technology Academic Research Center
Head Office	:	17-2, Shin Yokohama 3-chome,Kohoku-ku,Yokohama 222-0033 Japan
President & CEO	:	Katsuhiro Shimohigashi
Capital	:	440 million yen
Established	:	December 28, 1995
Shareholders	:	Fujitsu Semiconductor Limited, Panasonic Corporation, Renesas Electronics Corporation, Rohm Co., Ltd., Sanyo Semiconductor Co., Ltd., Seiko Epson Corporation, Sharp Corporation, Sony Corporation, Toshiba Corporation

About Jedat, Inc.

Jedat offers the custom LSI design environment “Alpha-SX series” that automates custom LSI design such as analog LSI, power device, LCD driver and memory. With the floorplan function (hierarchical operation, pin assignment, power supply and bus routing, etc.) and the automatic placement and routing tool for custom layout, Alpha-SX has brought significant improvement to the area where automation was previously difficult. Individual point tools are integrated in a constraint driven environment, and providing results via accumulation and reuse of design know-how. Distribution partners are located in Seoul (Korea), Beijing and Shanghai (China), Hsinchu (Taiwan) and the U.S. West Coast. These partners provide the same experienced customer support as Jedat offers in Japan. Visit Jedat on the web at www.jedat.co.jp.

Headquarters	:	3-4-14 Higashi-Nihonbashi, Chuo-ku, 103-00104, Tokyo
Operations began	:	February 2, 2004
Capital	:	760,007,110 Japanese yen
President & CEO	:	Ishibashi, Shinichi
URL	:	https://www.newjedat.arum-net.com/eng
Business descriptions	:	Research, development and sales of EDA software for designing IC (Integrated Circuit) and FPD (Flat Panel Display); related consulting services

Click here for PDF version of the release. 

For more information, please contact here

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SoftJin announces the connection with HOTSCOPE
in the new release of NxDAT Defect Analysis Software

2011.3.1

The following is the summary of this annoucement.

SANTA CLARA, Calif. (USA) & BANGALORE, India – 24 February 2011 –SoftJin Technologies, a provider of customized automation software for Electronic Design and Manufacturing, today announced the enhanced version of NxDAT, its Defect Analysis software. NxDAT is widely used by Mask shops and Wafer foundries for efficient analysis of Defects identified by IC Photomask Inspection Systems.NxDAT, with its open Architecture, can be easily extended for analysis of defects identified by a variety of Inspection equipments including IC / FPD Mask Inspection Systems, Wafer Inspection Systems and Metrology Systems.

NxDAT combines Mask Inspection and Design Automation worlds by supporting correlation of mask defect data with CAD Layout data. SoftJin has now enhanced this feature by providing direct interface with HOTSCOPE Layout and Mask data Viewer. HOTSCOPE, an industry standard Layout and mask data viewer from Jedat Inc. (Japan), is capable of reading and displaying huge sized mask data quickly and accurately. With HOTSCOPE interface in NxDAT, user can navigate through the defect data in NxDAT and at the same time visualize the corresponding region of CAD data in HOTSCOPE, thus enabling design based defect criticality analysis.

About SoftJin

More information is available at
http://www.softjin.com/html_new/postlayout_eda_products_overview.html

Click here for PDF version of the release of SoftJin. 

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Jedat Supports iPDK

2011.1.20

Chuo-ku, Tokyo, January 20, 2011

Jedat, Inc. (JASDAQ:3841) today announced that its custom/analog design platform “Alpha-SX(R)” supports the interoperable process design kit (iPDK) of which IPL（Interoperable PDK Library）Alliance promotes standardization.

Jedat joined IPL Alliance in September, 2007, and has promoted standardization. By having supported iPDK, it enables designers of fabless and semiconductor companies rapid availability of PDKs for leading edge process technology in the best-in-class design environment of Jedat without being restricted by proprietary PDK files and database. As the effect of standardization, it allows semiconductor designers to reduce library development costs and improve effective reuse of design property.

iPDK includes symbols, parameterized cells, call back parameters, and technology files, and will be provided advanced technology quickly by foundries or semiconductor companies of IPL Alliance members. Jedat promotes the support of iPDK, and all applications from the front-end to the back-end are scheduled to be completed by the release version in March, 2011.

The benefits of IPL

Supports all tools that are compatible with Open Access database by single PDKSignificant reduction of development period and support cost of PDKFlexibility of developing custom/analog design flowReusability of design property

Alpha-SX iPDK I/F

About iPDK

February 2010, IPL announced the open standard for interoperable process design kit “iPDK”. By PDK standardization, it contributes to cost savings of analog / mixed-signal design. This open standard recommends parameterized cell library of “PyCell Studio” developed by Ciranova, one of the start-up members of IPL. IPL members can access information related to development and verification of iPDK.

About IPL Alliance

The IPL (Interoperable PDK Libraries) Alliance is an industry organization established to develop an interoperable eco-system for custom design by creating and promoting interoperable PDK standards. Current IPL Alliance members include Accelicon Technologies, Agilent Technologies, Alreta, Applied Wave Research (AWR), Ciranova, Coventor, Empyrean, GRID Simulation Technology, Helic, JEDAT, Juspertor, LFoundry, Magma Design Automation, Mephisto Design Automation, Micrologic Design Automation, Micro Magic, Parallel Engines, Sagantec, SpringSoft, STARC, STMicroelectronics, SynCira, Synopsys, Tanner EDA, TowerJazz, TSMC. Mentor Graphics and Pulsic are supporting members. For more information, please visit IPL Alliance web site at http://www.iplnow.com or contact info@iplnow.com

About Jedat, Inc.

Jedat offers the custom LSI design environment “Alpha-SX series” that automates custom LSI design such as analog LSI, power device, LCD driver and memory. With the floor plan function (hierarchical operation, pin assignment, and power supply and bus routing, etc.) and the automatic placement and routing tool for custom layout, Alpha-SX has brought significant improvement to the area where the automation was difficult so far. All of the tools are integrated in the constraint driven environment, and they provide a result in accumulation and reusing the design know-how. Distribution partners are located in Seoul (Korea), Beijing and Shanghai (China), Hsinchu (Taiwan) and the U.S. West Coast. These partners provide the same experienced customer support as Jedat offers in Japan. Visit Jedat on the Web at www.jedat.co.jp

Headquarters	:	2-26-5 Nihonbashi Ningyo-cho, Chuo-ku, 103-0013, Tokyo
Operations began	:	February 2, 2004
Capital	:	760,007,110 Japanese yen
President & CEO	:	Ishibashi, Shinichi
URL	:	https://www.newjedat.arum-net.com/eng
Business descriptions	:	Research, development and sales of EDA software for designing IC (Integrated Circuit) and FPD (Flat Panel Display); related consulting services

For more information, please contact here

Kenichi Tanaka, Corporate Planning Division, Jedat Inc.
Tel: +81-3-5847-0312

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Jedat announces “HOTSCOPE V7.5”
the world’s fastest display and analysis browser
for large scale LSI

2009.11.16

Chuo-ku, Tokyo, November 16, 2009 – Jedat, Inc. released the latest version of HOTSCOPE v7.5, the super-fast display and analysis browser of LSI layout data.
HOTSCOPE is the tool that indicates super large-scale LSI data which exceeds 100 gigabytes at high speed, and variously analyzes the data such as verification of the design data and specification of defective spots, etc. With miniaturization and complication of manufacturing process, the processing scale has traced the course of increase. HOTSCOPE has become the indispensable tool in all process from design to manufacturing of LSI.

HOTSCOPE v7.5 which has been released this time, the analysis features are mainly strengthened substantially. The main features are as follows:

1. Automatically generates the schematic from the layout data

(1) Equipotential line tracking capability on the layout pattern.
(2) Automatically recognizes cells & transistors, and generates the netlist.
(3) Automatically generates the schematic from the netlist.

With this features, it has been able to specify the defective spots of the layout compared with the circuit data. By relating between the circuit, layout and EB data that could not be ensured their consistency so far, the search efficiency such as narrowing down the failure cause has risen rapidly.

２. Efficiency improvement of the work in team between remote locations With remote display function, because group of worker on LAN can share the same display screen, while looking at the same screen, it has become possible even with when design locations are remotely-situated to assure the improvement of efficiency of team job.

3. GDS conversion from profile line of SEM (scanning electron microscope) image With this function, it extracts the wafer pattern shape, compares and collates with the design data, and calculates the areas. It is possible to devise the appropriate measures which is directed to mass production such as specification of the problem spot which originates in manufacturing and decision of manufacturing parameters, etc.

4. Link to the CMP simulator Depending upon the connection with the CMP simulator, it has become possible to work the integrated sets of operations such as result indication of the CMP simulator (CMP-Designer) and indication analysis of cross section profile. With this, it becomes more efficient to analyze the thickness distribution by the CMP polishing in high accuracy, and can perform optimization of the CMP process and the design rule.

By the above-mentioned new features, it can achieve a great efficiency improvement of verification process at each stage of work flow: layout design, mask design, manufacturing inspection and defective analysis, etc. We will meet the needs of reducing the semiconductor product life cycle and quality improvement that should rises more and more in the future.

Equipotential line tracking

Cell recognition

GDS conversion from profile line of image

CMP-Designer connection

About HOTSCOPE:

The world best performance high speed display and analysis browser which is directed to the large-scale LSI layout data. In recent years, the design data scale is tracking the course of increase depending upon high function, high integration and miniaturization. In addition, as for final data, it is not unusual to reach tera-bite class by OPC processing and inserting of dummy patterns.

Because of this reason, it has become important problems to treat the data in the process of display, confirmation and verification job of LSI. To solve these problems, HOTSCOPE has been greatly made the mask verification process of state-of-the-art LSI more efficient by high-speed displaying of the data with various device formats including GDSII format and other photolithography machine format, and having an abundant variety of verification function. We have already abundant adoption results in a lot of domestic and foreign semiconductor and mask companies.

[Features]

• Super-large-scale data that exceeds 100G byte will be opened in a very short time, and display at high speed
• Provide integrated analysis of LSI data by enhancing various analysis features
• Support multi format (GDS2, MEBES, HL, VSB8/11/12, JEOL, MIC, OASIS, MALY, P10, LEF/DEF, Calibre/Error Log)
• Support multi platform
• Advanced analysis features (Various measurement functions, Image processing, Image calculation function, equipotential line tracking capability, schematic display, etc.)
• API that facilitates interface development with various software and devices
• High-level script language AXEL that enables GUI customization

About Jedat Inc.

Headquarters	:	6-6 Nihonbashi Kobuna-cho, Chuo-ku, 103-0024, Tokyo
Operations began	:	February 2, 2004
Capital	:	760,007,110 Japanese yen
President & CEO	:	Ishibashi, Shinichi
URL	:	https://www.newjedat.arum-net.com/eng
Business descriptions	:	Research, development and sale of EDA software for designing IC (Integrated Circuit) and FPD (Flat Panel Display); related consulting services

For more information, please contact here

【 Media 】
Oota, Hirohiko, Corporate Planning Division, Jedat Inc.
Tel: +81-3-5847-0312

【 Customer 】
Inoue, Masaru, DFM Technical Marketing Department, Jedat Inc.
Tel: +81-3-5847-0314

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Jedat brings out integrated circuit design tool “C³” (Circuit-Cube)

2009.10.20

Chuo-ku, Tokyo, October 20, 2009 – Jedat, Inc. brings out an integrated circuit design tool: C³ (Circuit-Cube).

C³ is the next generation circuit design tool which seamlessly integrates front-end design environment: schematic entry, simulation control and waveform display & analysis. As a result, it greatly improves design efficiency, and makes it possible to accumulate and reuse the schematic data and design know-how.

Since the designer does circuit design and simulation analysis based on each individual scenario (design procedure) so far, schematics, circuit constraint information and verification scenarios have not been accumulated as common know-how. Therefore, circuit design is depending heavily on an individual skill.

By making database of these know-how as design properties, C³ increases the design efficiency and enables easily sharing the design know-how, and reuse the design properties. Consequently, the circuit design quality is surely improved and the circuit design and verification cycle can be greatly shortened.

Furthermore, because C³ automatically generates the layout constraint from circuit constraint information, it becomes possible to achieve the high quality layout design as well as prevention of re-design from layout process, and shorten the overall TAT and improve the design quality from circuit design to layout design.

C³ has the following features.

• Achieves seamless design and verification work by integrating schematic entry, simulation control and waveform analysis.
• Design knowhow is made to the database and recycled.
  • Circuit information
  • Circuit constraint
  • Verification scenario
• Layout constraint is generated automatically from circuit constraint.
  • Consistent design environment from circuit through layout
  • Reduce respin of layout design ◦Improve layout quality
  • Generate and verify constraints of EM/IRDrop etc.
• Efficient simulation control and result analysis
  • Operation point information is fed back to the schematic, and the saturation condition is confirmed visually.
  • Easy to control simulation execution such as analysis type and corner setting, etc.
  • Easy definition and automatic measurement of waveform measurement condition by exclusive function GUI
  • Confirmation of a measurement result and easy detection of critical corner by display list of simulation result
  • Easy to make documents like simulation result and the result list of measurement, etc.
• Fast display, measurement and analysis of large-scale waveform data

C³ execution screen

Target specification setting scenario

Easy detection of critical corner 

P result verification and display on Asca 

About Jedat Inc.

Headquarters	:	6-6 Nihonbashi Kobuna-cho, Chuo-ku, 103-0024, Tokyo
Operations began	:	February 2, 2004
Capital	:	760,007,110 Japanese yen
President & CEO	:	Ishibashi, Shinichi
URL	:	https://www.newjedat.arum-net.com/eng
Business descriptions	:	Research, development and sales of EDA software for designing IC (Integrated Circuit) and FPD (Flat Panel Display); related consulting services

For more information, please contact here

【 Media 】
Oota, Hirohiko, Corporate Planning Division, Jedat Inc.
Tel: +81-3-5847-0312

【 Customer 】
Kakinoki, Toshihiko, Technical Marketing Division, Jedat Inc.
Tel: +81-3-5847-0314

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Jedat launches the world’s first 3D capacitance extraction tool for flat-panel display

2009.10.9

Chuo-ku, Tokyo, October 9, 2009 – Jedat, Inc. launches the 3D wiring capacitance extraction tool for flat panel display: FineQap.

So far, the optimal wiring characteristic of flat-panel display can be secured enough if only the wiring resistance is paid attention, but it becomes impossible to disregard the influence of the wiring capacity due to the trends of large scale and high speed motion of flat-panel displays.

However, there were practical problems in existing capacitance extraction tool.

• a). Can not obtain necessary and sufficient accuracy from flat-panel display
• b). Can not extract the capacity of long wiring with several centimeters or more.

By using FineQap, it has become possible to extract 3D wiring capacitance of flat-panel display for the first time which is becoming large scale and high speed, and secure an enough display quality without making them for trial purposes.

FineQap has achieved the extraction of a high accuracy wiring capacitance for the feature of flat-panel display as the following that had not been able to be done by an existing tool.

• Long wiring with minute width and minute height
• Wirings other than orthogonalization system (diagonal wiring)
• Non-planarization process
• Model without grand substrate

FineQap runs on Alpha-SX FineCreator (Jedat’s design environment for flat-panel display), and extracts wiring capacitance at high speed by specifying the parameter of cross section structure.

Image chart of 3D wiring capacitance extraction model

3D wiring and grid chart of target for calculation

Extraction result: Capacity density is displayed on the surface of wiring

About Jedat Inc.

Headquarters	:	6-6 Nihonbashi Kobuna-cho, Chuo-ku, 103-0024, Tokyo
Operations began	:	February 2, 2004
Capital	:	760,007,110 Japanese yen
President & CEO	:	Ishibashi, Shinichi
URL	:	https://www.newjedat.arum-net.com/eng
Business descriptions	:	Research, development and sales of EDA software for designing IC (Integrated Circuit) and FPD (Flat Panel Display); related consulting services

For more information, please contact here

【 Media 】
Oota, Hirohiko, Corporate Planning Division, Jedat Inc.
Tel: +81-3-5847-0312

【 Customer 】
Nobuto, Ono, Technical Marketing Division, Jedat Inc.
Tel: +81-3-5847-0314

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Notification of nonbusiness day and interruption of telephone / fax service due to Jedat headquarters relocation.

2009.8.11

Dear Customer:

We would like to express my thanks for your loyal patronage.
Jedat headquarters office will be closed for the relocation as the following.

And the telephone/fax will be interrupted by constructing the exchanger for the following period.

We are very sorry to cause you inconvenience.
We humbly ask for your understanding and cooperation.

Note:

• Nonbusiness day
  • Friday, August 14, 2009
• Telephone and fax service interruption period
  • from 15:00, August 14, 2009 to 15:00, August 16, 2009

Your continued support and contribution is greatly appreciated.
Sincerely yours,
Corporate Planning Division
Jedat,Inc.

For more information, please contact here

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Notification of company relocation

2009.7.30

Dear all:

We are pleased to announce that Jedat Inc. is scheduled to relocate its headquarter office on August 15, 2009. This relocation was made to accommodate rapid market growth and to improve our service for customers.

The new address is as follows. Phone number and FAX number have not changed.

Address	:	Nittsu Ningyo-cho Bldg. 2-26-5, Nihonbashi Ningyo-cho, Chuo-ku, Tokyo 103-0013 Japan
TEL	:	+81-3-5847-0312
FAX	:	+81-3-5847-0315
URL	:	https://www.newjedat.arum-net.com/eng

We look forward to seeing you in the new office.

For more information, please contact here
Your continued support and contribution is greatly appreciated.

Truly yours,
Jedat Inc.

Access Map:

Transportation:

• One minute on foot from Exit A3 of Tokyo Metro & Toei Subway Ningyo-cho Station
• Five minutes on foot from Exit 7 of the Tokyo Metro Suitengumae Station
• Six minutes on foot from Exit A2 of the Toei Subway Hamacho Station

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Jedat, DaouXilicon and Legend Design Jointly Provide the True LCD Panel Simulation

2009.7.23

SANTA CLARA, Calif.-Jedat Inc., DaouXilicon Inc., and Legend Design Technology Inc. today announced a breakthrough technology for LCD Panel Simulation with the release of their joint solution: LCD design environment Asca, WLModeler and Simface from Jedat, LCD modeling module ExpertLCD from DaouXilicon, and LCD simulator MSIM from Legend Design Technology. The joint solution from three partnered companies enables accurate simulation of LCD panel with time variant LC model. Through the seamless link between MSIM LCD circuit analysis and ExpertLCD model extraction, LCD designers can analyze the simulation results to spy those unwelcome cross-talk, flicker and uniformity issues.

To improve the productivity in LCD panel design and simulation, Jedat has provided a complete design environment consisting of (1) Asca for schematic capture, which defines pixel equivalent circuit including dynamic capacitance of liquid crystal. (2) WLModeler for netlist reduction, which generates the reduced LCD panel netlist for circuit simulation. The wire RC back-annotation is also available. (3) Simface for simulator interface, which creates stimuli, conditions and controls for circuit simulation. Both Legend’s MSIM circuit simulator and DaouXilicon’s ExpertLCD modeling module have been integrated into Jedat’s package to become a total solution.

In Liquid Crystal Display (LCD), the LC (Liquid Crystal) is aligned to the direction of electric field in pixel because of LC’s anisotropic characteristic. By simulating the time-dependent LC behavior and transmittance of a pixel, DaouXilicon’s ExpertLCD accurately extracts dynamic capacitance (Clc) between pixel and common electrode. ExpertLCD’s excellent performance has been well proven in display market for decades. Since no other circuit simulators have considered dynamic capacitance for high accuracy yet, the joint solution of ExpertLCD and MSIM circuit simulator will be the first to consider the dynamic capacitance and optical characteristic at each pixel. The whole package will enable users to optimize LCD panel design in both optical and electrical aspects simultaneously.

Each pixel in LCD cell is normally modeled by a TFT, a storage capacitor and a LC capacitor (Clc). Conventionally, the LC capacitor is modeled statically by polynomial or behavior equations. However, the static model cannot reflect the reality of time-variation during simulation. To enable the dynamic modeling, Legend’s MSIM circuit simulator has successfully built the protocol for co-simulation with the LC capacitor model extraction module from DaouXilicon. Periodically, MSIM will pass the simulation conditions to LC capacitor model API and then retrieve the updated LC capacitor model based upon the field solver. This complete co-simulation toolset has been thoroughly proven accurate and efficient. Product quality in LCD industry is very critical, with the high expectations for brightness, contrast, response time and power consumption. Our joint solution for accurate and fast LCD panel simulation has enabled not only detecting possible malfunctions but also optimizing various design parameters in product development stage. We have all committed to provide a premier solution with highest quality to meet the demands in LCD market.

PDF file is attached to the following. 

For more information, please contact here

Jedat Inc.
https://www.newjedat.arum-net.com
Motoo Miyake
+81-3-5847-0314

DaouXilicon Inc.
http://www.daouxilicon.com
DW Kang
Manager
+82-70-7010-8380

Legend Design Technology Inc.
http://www.LegendDesign.com
Jane Wei
Manager
408-748-8888 x234

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