FineVolt – 株式会社ジーダット https://www.newjedat.arum-net.com/en Mon, 31 Oct 2022 03:36:26 +0000 en-US hourly 1 https://www.newjedat.arum-net.com/wp-content/uploads/2022/05/cropped-super-big-icon-32x32.jpg FineVolt – 株式会社ジーダット https://www.newjedat.arum-net.com/en 32 32 GT-Router: Presentation video https://www.newjedat.arum-net.com/en/gt-router_presentation/ Thu, 19 May 2022 14:17:08 +0000 https://www.jedat.co.jp/?page_id=18862 GT-Router: Presentation video [contact-form-7]

]]> GT-Router: Operation flow https://www.newjedat.arum-net.com/en/gt-router_flow/ Thu, 19 May 2022 14:13:24 +0000 https://www.jedat.co.jp/?page_id=18860 GT-Router: Operation flow [contact-form-7]

]]> FineVolt https://www.newjedat.arum-net.com/en/finevolt/ Thu, 19 May 2022 23:04:56 +0000 https://www.jedat.co.jp/?page_id=18858 FineVolt [contact-form-7]

]]> Whitepaper https://www.newjedat.arum-net.com/en/resource/whitepaper/ Wed, 16 Mar 2022 13:42:03 +0000 https://www.jedat.co.jp/?page_id=11692 Whitepaper

In preparation

]]> Presentation https://www.newjedat.arum-net.com/en/resource/presentation/ Wed, 16 Mar 2022 13:36:09 +0000 https://www.jedat.co.jp/?page_id=11687 Presentation

In preparation

]]> Videos https://www.newjedat.arum-net.com/en/resource/movie/ Wed, 16 Mar 2022 07:00:50 +0000 https://www.jedat.co.jp/?page_id=11548 Videos

FineFFP： Automatically mask the Aperture Area for free form panel

Place BM (Black Matrix) figures into the current cell at the apertures of the pixels which cross the borderline of the Active Area.

FineFFP: GIP Automatic placement & Routing for free form panel

GIP cells are automatically placed around the panel according to the template figure, and wiring is also performed between GIP cells.

*GIP Cell: Gate In Panel Cell

FineFFP : HID area Automatic Routing for free form panel

Automatically route gate lines from the left side and right side and data lines from topside to bottom side in the holes of the panel while avoiding the Keep Out Area.

*HID: Hole In Display

FineFFP : Notch area Automatic Routing for free form panel

Automatically route gate wiring from left to right of the notch area according to the template figure in the notch area.

PowerVolt

Layout editor platform for flat panel display design. It allows reduction of design cycle time and quality improvement by special features.

FineArts

Layout editor platform for flat panel display design. It allows reduction of design cycle time and quality improvement by special features.

Simplify

Auto routing capability for flat panel displays of any shape for mobile/IoT/automotive applications.

FineAcres/Qap

High speed and high accuracy resistance/capacitance extraction tool for long and fat wires between pixels and drivers of flat panel displays.

FineVolt

Voltage drop and current density analysis for OLED. The built-in high-speed solver allows verifying the full panel scale data.

GT-Router: Operation flow

The constraint-driven (EM/IR Drop/Noise) power router which minimizes the chip size. Achieved by assigning wire topology and congestion-aware technology including slot insertion.

GT-Router: Presentation video

The constraint-driven custom power line router which can generate reliable and robust slot power line based on the design requirements of each block.

HOTSCOPE: Net trace and schematic generation

It allows designers to generate the equivalent schematic from the layout data by running equipotential net tracing capabilities. After tracing, it makes possible to provide cross-probing capabilities between schematic and layout.

HOTSCOPE: 3D cross-section viewing

After specifying the locations on the layout pattern, 3D structure is displayed and designers can observe the data while rotating in the horizontal and vertical directions. It also allows a variety of analysis functions, such as by the equipotential net tracing and 3D measurement function.

HOTSCOPE: Resistance calculation

After specifying the locations on the layout pattern, 3D structure is displayed and designers can observe the data while rotating in the horizontal and vertical directions. It also allows a variety of analysis functions, such as by the equipotential net tracing and 3D measurement function.

]]> Layout Parameter Extraction and Analysis Tool https://www.newjedat.arum-net.com/en/fpd_design/parameter_extract-2/ Sat, 26 Feb 2022 12:01:39 +0000 https://www.jedat.co.jp/?page_id=10528 Layout Parameter Extraction and Analysis Tool

Total support for a wide range of characteristic analysis from pixel cells to the entire panel

  • High-accuracy parasitic resistance and capacitance extraction using 2D and 3D solvers
    High-speed, high-accuracy parasitic extraction for pixel cell layout from top-level panel wiring
  • Provides analysis solutions for each FPD specific field such as voltage drop analysis

Resistance Extraction Tool for FPD

SX-Meister FineAcres

■High-speed and high-accuracy extraction of resistance values from figures of all shapes

  • High-speed calculation of wiring resistance value by FEM
    Supports complex shapes including any-angle figures, arcs, and slits
  • Electrode resistance distribution measurement by multipoint continuous measurement

Capacitance Extraction Tool for FPD

SX-Meister FineQap

■Full-panel scale high-accuracy, high-speed wiring capacitance extraction

  • BEM 3D capacitance extraction engine
  • Parasitic extraction of wiring for large-scale and high-aspect ratio panels
    Extracted model generation from layout data and wiring section parameters
    Supports any angle wiring and multi-layer wiring
    Supports non-flattening process
    Supports floating metal
  • Check process structure and extraction results by 3D viewer

Resistance and Capacitance Extraction Tool for FPD

SX-Meister FineResQ

■Extraction of wiring resistance and capacitance with high accuracy and high speed on a panel scale

  • Optimal algorithm that enables high-accuracy and high-speed extraction of resistance and capacitance
  • Parasitic extraction of large-scale and high-aspect ratio panel wiring
  • Outputs wiring parasitic information to support circuit analysis
  • Applicable to characteristic analysis of various touch panels

Voltage Drop and Current Density Analysis Tool for OLED Panels and Lighting Design

SX-Meister FineVolt

■Voltage Drop and Current Density Analysis Tool for OLED Panels and Lighting Design

  • Calculates and displays the voltage drop and current density distribution of the wiring inside the panel
  • Calculates the current for each pixel in consideration of the voltage drop, and displays the current density of each pixel
  • Automatic recognition of wiring and devices
  • Device model
    Spice model (aSi / LTPS TFT)
    Impoert I-V characteristics (TFT/organic EL layer)

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