Welcome to Jedat at DAC2019
|Exhibition name||Design Automation Conference 56th|
|Exhibit Hours||Monday, June 3 10:00am – 6:00pm|
Tuesday, June 4 10:00am – 6:00pm
Wednesday, June 5 10:00am – 6:00pm
|Exhibition Site||LAS VEGAS CONVENTION CENTER NV|
|Booth No.||# 560|
|Design / IP|
|“ Practical Cell Based Analog Design MethodologyⅡ (AnaCell) ”|
Design / IP Track Session 58
Every Joule Counts
WEDNESDAY June 05, 1:30pm – 3:00pm
|Demo reservation||Please let the following demo reservation : Please click here|
Custom LSI design tool which enables the inheritance of design intent and know-how of experience
Circuit design platform includes the new methodology of analog cell level design which improve productivity and reusable and standardization of Analog design.
This time we present auto bias setting which improves the AnaCell efficiency.
PowerVolt helps to verify the robustness and ESD with powerline which is complicated in Memory, Driver etc in early floorplan to signoff phase because it only needs the GDS data without netlist.