DownloadEDA Tools of the Partners for SoC Design
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License Management |
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HPC environment integrated operation middleware ShareTask |
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RTL Design Digital Implementation and Verification |
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SDC Verification/SDC Generation/SDC Management (promotion,merge) |
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RTL Design Digital Implementation and Verification |
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Generate high quality SystemVerilog models from analog circuits and verify |
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RTL Design Low-power Design |
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RTL high accuracy and high speed power consumption analysis |
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SoC Floorplan |
Dataflow analyzer and floorplan exploration system |
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SPICE Modeling Analog ,Chip-level Verification |
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SPICE Simulator, Modelling tool, Noise measurement |
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Analog Implementation and Verification |
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Integrated Circuit design and layout design system |
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IP |
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The most-advanced process IP: PLL/SerDes/LVDS-IO |
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IP |
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Verification IP Tool set (USB~AMBA over80) |
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Board Implementation |
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High wiring rate topology-based auto routing |
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EMC Verification |
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EMC Virtual Laboratory (RE/CE/RI/CI) |
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Photomask Verification |
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Analysis browser for DFM/Photomask verification |
